#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <time.h>

enum Core6502Instructions
{
	CPU_INST_BRK = 0,          // 0x00 : BRK
	CPU_INST_ORA_IND_X,        // 0x01 : ORA (IND,X)
	CPU_INST_BAD_02H,          // 0x02 : BAD INSTRUCTION
	CPU_INST_SLO_IND_X,        // 0x03 : SLO (IND,X)
	CPU_INST_BAD_04H,          // 0x04 : BAD INSTRUCTION
	CPU_INST_ORA_ZP,           // 0x05 : ORA $ZZ
	CPU_INST_ASL_ZP,           // 0x06 : ASL $ZZ
	CPU_INST_SLO_ZP,           // 0x07 : SLO $ZZ
	CPU_INST_PHP,              // 0x08 : PHP
	CPU_INST_ORA_IMM,          // 0x09 : ORA #$nn
	CPU_INST_ASL_ACCUM,        // 0x0A : ASL A
	CPU_INST_BAD_0BH,          // 0x0B : BAD INSTRUCTION
	CPU_INST_BAD_0CH,          // 0x0C : BAD INSTRUCTION
	CPU_INST_ORA_ABS,          // 0x0D : ORA $hhll
	CPU_INST_ASL_ABS,          // 0x0E : ASL $hhll
	CPU_INST_SLO_ABS,          // 0x0F : BAD INSTRUCTION
	CPU_INST_BPL_REL,          // 0x10 : BPL REL
	CPU_INST_ORA_IND_Y,        // 0x11 : ORA (IND),Y
	CPU_INST_BAD_12H,          // 0x12 : BAD INSTRUCTION
	CPU_INST_SLO_IND_Y,        // 0x13 : SLO (IND),Y
	CPU_INST_BAD_14H,          // 0x14 : BAD INSTRUCTION
	CPU_INST_ORA_ZP_X,         // 0x15 : ORA $ZZ,X
	CPU_INST_ASL_ZP_X,         // 0x16 : ASL $ZZ,X
	CPU_INST_SLO_ZP_X,         // 0x17 : SLO $ZZ,X
	CPU_INST_CLC,              // 0x18 : CLC
	CPU_INST_ORA_ABS_Y,        // 0x19 : ORA $hhll,Y
	CPU_INST_BAD_1AH,          // 0x1A : BAD INSTRUCTION
	CPU_INST_SLO_ABS_Y,        // 0x1B : SLO $hhll,Y
	CPU_INST_BAD_1CH,          // 0x1C : BAD INSTRUCTION
	CPU_INST_ORA_ABS_X,        // 0x1D : ORA $hhll,X
	CPU_INST_ASL_ABS_X,        // 0x1E : ASL $hhll,X
	CPU_INST_SLO_ABS_X,        // 0x1F : SLO $hhll,X
	CPU_INST_JSR_ABS,          // 0x20 : JSR $hhll
	CPU_INST_AND_IND_X,        // 0x21 : AND (IND,X)
	CPU_INST_BAD_22H,          // 0x22 : BAD INSTRUCTION
	CPU_INST_BAD_23H,          // 0x23 : BAD INSTRUCTION
	CPU_INST_BIT_ZP,           // 0x24 : BIT $ZZ
	CPU_INST_AND_ZP,           // 0x25 : AND $ZZ
	CPU_INST_ROL_ZP,           // 0x26 : ROL $ZZ
	CPU_INST_BAD_27H,          // 0x27 : BAD INSTRUCTION
	CPU_INST_PLP,              // 0x28 : PLP
	CPU_INST_AND_IMM,          // 0x29 : AND #$nn
	CPU_INST_ROL_ACCUM,        // 0x2A : ROL A
	CPU_INST_BAD_2BH,          // 0x2B : BAD INSTRUCTION
	CPU_INST_BIT_ABS,          // 0x2C : BIT $hhll
	CPU_INST_AND_ABS,          // 0x2D : AND $hhll
	CPU_INST_ROL_ABS,          // 0x2E : ROL $hhll
	CPU_INST_BAD_2FH,          // 0x2F : BAD INSTRUCTION
	CPU_INST_BMI_REL,          // 0x30 : BMI REL
	CPU_INST_AND_IND_Y,        // 0x31 : AND (IND),Y
	CPU_INST_BAD_32H,          // 0x32 : BAD INSTRUCTION
	CPU_INST_BAD_33H,          // 0x33 : BAD INSTRUCTION
	CPU_INST_BAD_34H,          // 0x34 : BAD INSTRUCTION
	CPU_INST_AND_ZP_X,         // 0x35 : AND $ZZ,X
	CPU_INST_ROL_ZP_X,         // 0x36 : ROL $ZZ,X
	CPU_INST_BAD_37H,          // 0x37 : BAD INSTRUCTION
	CPU_INST_SEC,              // 0x38 : SEC
	CPU_INST_AND_ABS_Y,        // 0x39 : AND $hhll,Y
	CPU_INST_BAD_3AH,          // 0x3A : BAD INSTRUCTION
	CPU_INST_BAD_3BH,          // 0x3B : BAD INSTRUCTION
	CPU_INST_BAD_3CH,          // 0x3C : BAD INSTRUCTION
	CPU_INST_AND_ABS_X,        // 0x3D : AND $hhll,X
	CPU_INST_ROL_ABS_X,        // 0x3E : ROL $hhll,X
	CPU_INST_BAD_3FH,          // 0x3F : BAD INSTRUCTION
	CPU_INST_RTI,              // 0x40 : RTI
	CPU_INST_EOR_IND_X,        // 0x41 : EOR (IND,X)
	CPU_INST_BAD_42H,          // 0x42 : BAD INSTRUCTION
	CPU_INST_SRE_IND_X,        // 0x43 : SRE (IND,X)
	CPU_INST_BAD_44H,          // 0x44 : BAD INSTRUCTION
	CPU_INST_EOR_ZP,           // 0x45 : EOR $ZZ
	CPU_INST_LSR_ZP,           // 0x46 : LSR $ZZ
	CPU_INST_SRE_ZP,           // 0x47 : SRE $ZZ
	CPU_INST_PHA,              // 0x48 : PHA
	CPU_INST_EOR_IMM,          // 0x49 : EOR #$nn
	CPU_INST_LSR_ACCUM,        // 0x4A : LSR A
	CPU_INST_BAD_4BH,          // 0x4B : BAD INSTRUCTION
	CPU_INST_JMP_ABS,          // 0x4C : JMP $hhll
	CPU_INST_EOR_ABS,          // 0x4D : EOR $hhll
	CPU_INST_LSR_ABS,          // 0x4E : LSR $hhll
	CPU_INST_SRE_ABS,          // 0x4F : SRE $hhll
	CPU_INST_BVC_REL,          // 0x50 : BVC REL
	CPU_INST_EOR_IND_Y,        // 0x51 : EOR (IND),Y
	CPU_INST_BAD_52H,          // 0x52 : BAD INSTRUCTION
	CPU_INST_SRE_IND_Y,        // 0x53 : SRE (IND),Y
	CPU_INST_BAD_54H,          // 0x54 : BAD INSTRUCTION
	CPU_INST_EOR_ZP_X,         // 0x55 : EOR $ZZ,X
	CPU_INST_LSR_ZP_X,         // 0x56 : LSR $ZZ,X
	CPU_INST_SRE_ZP_X,         // 0x57 : SRE $ZZ,X
	CPU_INST_CLI,              // 0x58 : CLI
	CPU_INST_EOR_ABS_Y,        // 0x59 : EOR $hhll,Y
	CPU_INST_BAD_5AH,          // 0x5A : BAD INSTRUCTION
	CPU_INST_SRE_ABS_Y,        // 0x5B : SRE $hhll,Y
	CPU_INST_BAD_5CH,          // 0x5C : BAD INSTRUCTION
	CPU_INST_EOR_ABS_X,        // 0x5D : EOR $hhll,X
	CPU_INST_LSR_ABS_X,        // 0x5E : LSR $hhll,X
	CPU_INST_SRE_ABS_X,        // 0x5F : SRE $hhll,X
	CPU_INST_RTS,              // 0x60 : RTS
	CPU_INST_ADC_IND_X,        // 0x61 : ADC ($ZZ,X)
	CPU_INST_BAD_62H,          // 0x62 : BAD INSTRUCTION
	CPU_INST_RRA_IND_X,        // 0x63 : RRA ($ZZ,X)
	CPU_INST_BAD_64H,          // 0x64 : BAD INSTRUCTION
	CPU_INST_ADC_ZP,           // 0x65 : ADC $ZZ
	CPU_INST_ROR_ZP,           // 0x66 : ROR $ZZ
	CPU_INST_RRA_ZP,           // 0x67 : RRA $ZZ
	CPU_INST_PLA,              // 0x68 : PLA
	CPU_INST_ADC_IMM,          // 0x69 : ADC #$nn
	CPU_INST_ROR_ACCUM,        // 0x6A : ROR A
	CPU_INST_BAD_6BH,          // 0x6B : BAD INSTRUCTION
	CPU_INST_JMP_INDIR,        // 0x6C : JMP ($hhll)
	CPU_INST_ADC_ABS,          // 0x6D : ADC $hhll
	CPU_INST_ROR_ABS,          // 0x6E : ROR $hhll
	CPU_INST_RRA_ABS,          // 0x6F : RRA $hhll
	CPU_INST_BVS_REL,          // 0x70 : BVS REL
	CPU_INST_ADC_IND_Y,        // 0x71 : ADC ($ZZ),Y
	CPU_INST_BAD_72H,          // 0x72 : BAD INSTRUCTION
	CPU_INST_RRA_IND_Y,        // 0x73 : RRA ($ZZ),Y
	CPU_INST_BAD_74H,          // 0x74 : BAD INSTRUCTION
	CPU_INST_ADC_ZP_X,         // 0x75 : ADC $ZZ,X
	CPU_INST_ROR_ZP_X,         // 0x76 : ROR $ZZ,X
	CPU_INST_RRA_ZP_X,         // 0x77 : RRA $ZZ,X
	CPU_INST_SEI,              // 0x78 : SEI
	CPU_INST_ADC_ABS_Y,        // 0x79 : ADC $hhll,Y
	CPU_INST_BAD_7AH,          // 0x7A : BAD INSTRUCTION
	CPU_INST_RRA_ABS_Y,        // 0x7B : RRA $hhll,Y
	CPU_INST_BAD_7CH,          // 0x7C : BAD INSTRUCTION
	CPU_INST_ADC_ABS_X,        // 0x7D : ADC $hhll,X
	CPU_INST_ROR_ABS_X,        // 0x7E : ROR $hhll,X
	CPU_INST_RRA_ABS_X,        // 0x7F : RRA $hhll,X
	CPU_INST_BAD_80H,          // 0x80 : BAD INSTRUCTION
	CPU_INST_STA_IND_X,        // 0x81 : STA (IND,X)
	CPU_INST_BAD_82H,          // 0x82 : BAD INSTRUCTION
	CPU_INST_BAD_83H,          // 0x83 : BAD INSTRUCTION
	CPU_INST_STY_ZP,           // 0x84 : STY $ZZ
	CPU_INST_STA_ZP,           // 0x85 : STA $ZZ
	CPU_INST_STX_ZP,           // 0x86 : STX $ZZ
	CPU_INST_BAD_87H,          // 0x87 : BAD INSTRUCTION
	CPU_INST_DEY,              // 0x88 : DEY
	CPU_INST_BAD_89H,          // 0x89 : BAD INSTRUCTION
	CPU_INST_TXA,              // 0x8A : TXA
	CPU_INST_BAD_8BH,          // 0x8B : BAD INSTRUCTION
	CPU_INST_STY_ABS,          // 0x8C : STY $hhll
	CPU_INST_STA_ABS,          // 0x8D : STA $hhll
	CPU_INST_STX_ABS,          // 0x8E : STX $hhll
	CPU_INST_BAD_8FH,          // 0x8F : BAD INSTRUCTION
	CPU_INST_BCC_REL,          // 0x90 : BCC REL
	CPU_INST_STA_IND_Y,        // 0x91 : STA (IND),Y
	CPU_INST_BAD_92H,          // 0x92 : BAD INSTRUCTION
	CPU_INST_SHA_IND_Y,        // 0x93 : SHA (IND),Y
	CPU_INST_STY_ZP_X,         // 0x94 : STY $ZZ,X
	CPU_INST_STA_ZP_X,         // 0x95 : STA $ZZ,X
	CPU_INST_STX_ZP_Y,         // 0x96 : STX $ZZ,Y
	CPU_INST_BAD_97H,          // 0x97 : BAD INSTRUCTION
	CPU_INST_TYA,              // 0x98 : TYA
	CPU_INST_STA_ABS_Y,        // 0x99 : STA $hhll,Y
	CPU_INST_TXS,              // 0x9A : TXS
	CPU_INST_BAD_9BH,          // 0x9B : BAD INSTRUCTION
	CPU_INST_BAD_9CH,          // 0x9C : BAD INSTRUCTION
	CPU_INST_STA_ABS_X,        // 0x9D : STA $hhll,X
	CPU_INST_BAD_9EH,          // 0x9E : BAD INSTRUCTION
	CPU_INST_SHA_ABS_X,        // 0x9F : SHA $hhll,X
	CPU_INST_LDY_IMM,          // 0xA0 : LDY #$nn
	CPU_INST_LDA_IND_X,        // 0xA1 : LDA (IND,X)
	CPU_INST_LDX_IMM,          // 0xA2 : LDX #$nn
	CPU_INST_BAD_A3H,          // 0xA3 : BAD INSTRUCTION
	CPU_INST_LDY_ZP,           // 0xA4 : LDY $ZZ
	CPU_INST_LDA_ZP,           // 0xA5 : LDA $ZZ
	CPU_INST_LDX_ZP,           // 0xA6 : LDX $ZZ
	CPU_INST_BAD_A7H,          // 0xA7 : BAD INSTRUCTION
	CPU_INST_TAY,              // 0xA8 : TAY
	CPU_INST_LDA_IMM,          // 0xA9 : LDA #$nn
	CPU_INST_TAX,              // 0xAA : TAX
	CPU_INST_BAD_ABH,          // 0xAB : BAD INSTRUCTION
	CPU_INST_LDY_ABS,          // 0xAC : LDY $hhll
	CPU_INST_LDA_ABS,          // 0xAD : LDA $hhll
	CPU_INST_LDX_ABS,          // 0xAE : LDX $hhll
	CPU_INST_BAD_AFH,          // 0xAF : BAD INSTRUCTION
	CPU_INST_BCS_REL,          // 0xB0 : BCS REL
	CPU_INST_LDA_IND_Y,        // 0xB1 : LDA (IND),Y
	CPU_INST_BAD_B2H,          // 0xB2 : BAD INSTRUCTION
	CPU_INST_BAD_B3H,          // 0xB3 : BAD INSTRUCTION
	CPU_INST_LDY_ZP_X,         // 0xB4 : LDY $ZZ,X
	CPU_INST_LDA_ZP_X,         // 0xB5 : LDA $ZZ,X
	CPU_INST_LDX_ZP_Y,         // 0xB6 : LDX $ZZ,Y
	CPU_INST_BAD_B7H,          // 0xB7 : BAD INSTRUCTION
	CPU_INST_CLV,              // 0xB8 : CLV
	CPU_INST_LDA_ABS_Y,        // 0xB9 : LDA $hhll,Y
	CPU_INST_TSX,              // 0xBA : TSX
	CPU_INST_BAD_BBH,          // 0xBB : BAD INSTRUCTION
	CPU_INST_LDY_ABS_X,        // 0xBC : LDY $hhll,X
	CPU_INST_LDA_ABS_X,        // 0xBD : LDA $hhll,X
	CPU_INST_LDX_ABS_Y,        // 0xBE : LDX $hhll,Y
	CPU_INST_BAD_BFH,          // 0xBF : BAD INSTRUCTION
	CPU_INST_CPY_IMM,          // 0xC0 : CPY #$nn
	CPU_INST_CMP_IND_X,        // 0xC1 : CMP (IND,X)
	CPU_INST_BAD_C2H,          // 0xC2 : BAD INSTRUCTION
	CPU_INST_BAD_C3H,          // 0xC3 : BAD INSTRUCTION
	CPU_INST_CPY_ZP,           // 0xC4 : CPY $ZZ
	CPU_INST_CMP_ZP,           // 0xC5 : CMP $ZZ
	CPU_INST_DEC_ZP,           // 0xC6 : DEC $ZZ
	CPU_INST_BAD_C7H,          // 0xC7 : BAD INSTRUCTION
	CPU_INST_INY,              // 0xC8 : INY
	CPU_INST_CMP_IMM,          // 0xC9 : CMP #$nn
	CPU_INST_DEX,              // 0xCA : DEX
	CPU_INST_BAD_CBH,          // 0xCB : BAD INSTRUCTION
	CPU_INST_CPY_ABS,          // 0xCC : CPY $hhll
	CPU_INST_CMP_ABS,          // 0xCD : CMP $hhll
	CPU_INST_DEC_ABS,          // 0xCE : DEC $hhll
	CPU_INST_BAD_CFH,          // 0xCF : BAD INSTRUCTION
	CPU_INST_BNE_REL,          // 0xD0 : BNE REL
	CPU_INST_CMP_IND_Y,        // 0xD1 : CMP (IND),Y
	CPU_INST_BAD_D2H,          // 0xD2 : BAD INSTRUCTION
	CPU_INST_BAD_D3H,          // 0xD3 : BAD INSTRUCTION
	CPU_INST_BAD_D4H,          // 0xD4 : BAD INSTRUCTION
	CPU_INST_CMP_ZP_X,         // 0xD5 : CMP $ZZ,X
	CPU_INST_DEC_ZP_X,         // 0xD6 : DEC $ZZ,X
	CPU_INST_BAD_D7H,          // 0xD7 : BAD INSTRUCTION
	CPU_INST_CLD,              // 0xD8 : CLD
	CPU_INST_CMP_ABS_Y,        // 0xD9 : CMP $hhll,Y
	CPU_INST_BAD_DAH,          // 0xDA : BAD INSTRUCTION
	CPU_INST_BAD_DBH,          // 0xDB : BAD INSTRUCTION
	CPU_INST_BAD_DCH,          // 0xDC : BAD INSTRUCTION
	CPU_INST_CMP_ABS_X,        // 0xDD : CMP $hhll,X
	CPU_INST_DEC_ABS_X,        // 0xDE : DEC $hhll,X
	CPU_INST_BAD_DFH,          // 0xDF : BAD INSTRUCTION
	CPU_INST_CPX_IMM,          // 0xE0 : CPX #$nn
	CPU_INST_SBC_IND_X,        // 0xE1 : SBC (IND,X)
	CPU_INST_BAD_E2H,          // 0xE2 : BAD INSTRUCTION
	CPU_INST_ISB_ZP_X,         // 0xE3 : ISB_ZP_X
	CPU_INST_CPX_ZP,           // 0xE4 : CPX $ZZ
	CPU_INST_SBC_ZP,           // 0xE5 : SBC $ZZ
	CPU_INST_INC_ZP,           // 0xE6 : INC $ZZ
	CPU_INST_ISB_ZP,           // 0xE7 : ISB $ZZ
	CPU_INST_INX,              // 0xE8 : INX
	CPU_INST_SBC_IMM,          // 0xE9 : SBC #$nn
	CPU_INST_NOP,              // 0xEA : NOP
	CPU_INST_BAD_EBH,          // 0xEB : BAD INSTRUCTION
	CPU_INST_CPX_ABS,          // 0xEC : CPX $hhll
	CPU_INST_SBC_ABS,          // 0xED : SBC $hhll
	CPU_INST_INC_ABS,          // 0xEE : INC $hhll
	CPU_INST_ISB_ABS,          // 0xEF : ISB $hhll
	CPU_INST_BEQ_REL,          // 0xF0 : BEQ REL
	CPU_INST_SBC_IND_Y,        // 0xF1 : SBC (IND),Y
	CPU_INST_BAD_F2H,          // 0xF2 : BAD INSTRUCTION
	CPU_INST_ISB_IND_Y,        // 0xF3 : ISB (IND),Y
	CPU_INST_BAD_F4H,          // 0xF4 : BAD INSTRUCTION
	CPU_INST_SBC_ZP_X,         // 0xF5 : SBC $ZZ,X
	CPU_INST_INC_ZP_X,         // 0xF6 : INC $ZZ,X
	CPU_INST_BAD_F7H,          // 0xF7 : ISB $ZZ,X
	CPU_INST_SED,              // 0xF8 : SED
	CPU_INST_SBC_ABS_Y,        // 0xF9 : SBC $hhll,Y
	CPU_INST_BAD_FAH,          // 0xFA : BAD INSTRUCTION
	CPU_INST_ISB_ABS_Y,        // 0xFB : ISB $hhll,Y
	CPU_INST_BAD_FCH,          // 0xFC : BAD INSTRUCTION
	CPU_INST_SBC_ABS_X,        // 0xFD : SBC $hhll,X
	CPU_INST_INC_ABS_X,        // 0xFE : INC $hhll,X
	CPU_INST_ISB_ABS_X         // 0xFF : ISB $hhll,X
};


static unsigned char rom[0x8000];


static void generate_test_code(void)
{
	unsigned char	op;
//	unsigned char	operand1;
//	unsigned char	operand2;
	int				i;

	i = 0;

	while (i < 0x7ff0)
	{
		op = rand() & 0xff;
		switch (op)
		{
			/* imm instructions */
			//case CPU_INST_BRK
			//case CPU_INST_PHP:
			//case CPU_INST_PLP:
			case CPU_INST_PHA:
			case CPU_INST_PLA:
			case CPU_INST_DEY:
			case CPU_INST_TAY:
			case CPU_INST_INY:
			case CPU_INST_INX:
			case CPU_INST_CLC:
			case CPU_INST_SEC:
			case CPU_INST_CLI:
			case CPU_INST_SEI:
			case CPU_INST_TYA:
			case CPU_INST_CLV:
			case CPU_INST_CLD:
			case CPU_INST_SED:
			case CPU_INST_TXA:
			case CPU_INST_TXS:
			case CPU_INST_TAX:
			case CPU_INST_TSX:
			case CPU_INST_DEX:
			case CPU_INST_NOP:
				rom[i++] = op;
				break;
/*
			// do not test these for now...
			case CPU_INST_BRK:
			case CPU_INST_JSR:
			case CPU_INST_RTI:
			case CPU_INST_RTS:
*/
			// zp instructions
			case CPU_INST_ORA_ZP:
			case CPU_INST_ASL_ZP:
			case CPU_INST_BIT_ZP:
			case CPU_INST_AND_ZP:
			case CPU_INST_ROL_ZP:
			case CPU_INST_EOR_ZP:
			case CPU_INST_LSR_ZP:
			case CPU_INST_ADC_ZP:
			case CPU_INST_ROR_ZP:
			case CPU_INST_STY_ZP:
			case CPU_INST_STA_ZP:
			case CPU_INST_STX_ZP:
			case CPU_INST_LDY_ZP:
			case CPU_INST_LDA_ZP:
			case CPU_INST_LDX_ZP:
			case CPU_INST_CPY_ZP:
			case CPU_INST_CMP_ZP:
			case CPU_INST_DEC_ZP:
			case CPU_INST_CPX_ZP:
			case CPU_INST_SBC_ZP:
			case CPU_INST_INC_ZP:
				rom[i++] = op;
				rom[i++] = rand() & 0xff;
				break;

			case CPU_INST_ORA_ZP_X:
			case CPU_INST_ASL_ZP_X:
			case CPU_INST_AND_ZP_X:
			case CPU_INST_ROL_ZP_X:
			case CPU_INST_EOR_ZP_X:
			case CPU_INST_LSR_ZP_X:
			case CPU_INST_ADC_ZP_X:
			case CPU_INST_ROR_ZP_X:
			case CPU_INST_STY_ZP_X:
			case CPU_INST_STA_ZP_X:
			case CPU_INST_LDY_ZP_X:
			case CPU_INST_LDA_ZP_X:
			case CPU_INST_CMP_ZP_X:
			case CPU_INST_DEC_ZP_X:
			case CPU_INST_SBC_ZP_X:
			case CPU_INST_INC_ZP_X:
			case CPU_INST_STX_ZP_Y:
				rom[i++] = op;
				rom[i++] = rand() & 0xff;
				break;

			case CPU_INST_ORA_ABS:
			case CPU_INST_ASL_ABS:
			case CPU_INST_BIT_ABS:
			case CPU_INST_AND_ABS:
			case CPU_INST_ROL_ABS:
			case CPU_INST_EOR_ABS:
			case CPU_INST_LSR_ABS:
			case CPU_INST_ADC_ABS:
			case CPU_INST_ROR_ABS:
			case CPU_INST_STY_ABS:
			case CPU_INST_STA_ABS:
			case CPU_INST_STX_ABS:
			case CPU_INST_LDY_ABS:
			case CPU_INST_LDA_ABS:
			case CPU_INST_LDX_ABS:
			case CPU_INST_CPY_ABS:
			case CPU_INST_CMP_ABS:
			case CPU_INST_DEC_ABS:
			case CPU_INST_CPX_ABS:
			case CPU_INST_SBC_ABS:
			case CPU_INST_INC_ABS:
				rom[i++] = op;
				rom[i++] = rand() & 0xff;
				rom[i++] = rand() & 0x07;
				break;

			case CPU_INST_ORA_ABS_X:
			case CPU_INST_ASL_ABS_X:
			case CPU_INST_AND_ABS_X:
			case CPU_INST_ROL_ABS_X:
			case CPU_INST_EOR_ABS_X:
			case CPU_INST_LSR_ABS_X:
			case CPU_INST_ADC_ABS_X:
			case CPU_INST_ROR_ABS_X:
			case CPU_INST_STA_ABS_X:
			case CPU_INST_LDY_ABS_X:
			case CPU_INST_LDA_ABS_X:
			case CPU_INST_CMP_ABS_X:
			case CPU_INST_DEC_ABS_X:
			case CPU_INST_SBC_ABS_X:
			case CPU_INST_INC_ABS_X:
				rom[i++] = op;
				rom[i++] = rand() & 0xff;
				rom[i++] = rand() & 0x07;
				break;

			case CPU_INST_ORA_ABS_Y:
			case CPU_INST_EOR_ABS_Y:
			case CPU_INST_AND_ABS_Y:
			case CPU_INST_ADC_ABS_Y:
			case CPU_INST_STA_ABS_Y:
			case CPU_INST_LDA_ABS_Y:
			case CPU_INST_LDX_ABS_Y:
			case CPU_INST_CMP_ABS_Y:
			case CPU_INST_SBC_ABS_Y:
				rom[i++] = op;
				rom[i++] = rand() & 0xff;
				rom[i++] = rand() & 0x07;
				break;

			case CPU_INST_ORA_IND_X:
			case CPU_INST_AND_IND_X:
			case CPU_INST_EOR_IND_X:
			case CPU_INST_ADC_IND_X:
			case CPU_INST_STA_IND_X:
			case CPU_INST_LDA_IND_X:
			case CPU_INST_CMP_IND_X:
			case CPU_INST_SBC_IND_X:
				rom[i++] = op;
				rom[i++] = rand() & 0xff;
				break;

			case CPU_INST_ORA_IND_Y:
			case CPU_INST_AND_IND_Y:
			case CPU_INST_EOR_IND_Y:
			case CPU_INST_ADC_IND_Y:
			case CPU_INST_STA_IND_Y:
			case CPU_INST_LDA_IND_Y:
			case CPU_INST_CMP_IND_Y:
			case CPU_INST_SBC_IND_Y:
				rom[i++] = op;
				rom[i++] = rand() & 0xff;
				break;

			case CPU_INST_ASL_ACCUM:
			case CPU_INST_ROL_ACCUM:
			case CPU_INST_LSR_ACCUM:
			case CPU_INST_ROR_ACCUM:
				rom[i++] = op;
				break;

			case CPU_INST_ORA_IMM:
			case CPU_INST_AND_IMM:
			case CPU_INST_EOR_IMM:
			case CPU_INST_ADC_IMM:
			case CPU_INST_LDY_IMM:
			case CPU_INST_LDX_IMM:
			case CPU_INST_LDA_IMM:
			case CPU_INST_CPY_IMM:
			case CPU_INST_CMP_IMM:
			case CPU_INST_CPX_IMM:
			case CPU_INST_SBC_IMM:
				rom[i++] = op;
				rom[i++] = rand() & 0xff;
				break;
		}
	}

	rom[0x7ffb] = 0x4c;
	rom[0x7ffc] = 0x00;
	rom[0x7ffd] = 0x80;
}


int main(void)
{
	FILE* fp;

	srand((unsigned) time(NULL));

	memset(rom, 0xea, sizeof(rom));
	
	generate_test_code();

	fp = fopen("testcode.bin", "wb");

	fwrite(rom,sizeof(rom),1,fp);
	fclose(fp);

	return 0;
}