BIT 7, (HL) (12 cycles)

CLK ADDR DATA /M1 /MREQ /IOREQ /WR /RD /REFSH /BUSACK /HALT
 1   10   FF   0   1     1      1   1   1      1       1
 0   10   CB   0   0     1      1   0   1      1       1
 1   10   CB   0   0     1      1   0   1      1       1
 0   10   CB   0   0     1      1   0   1      1       1
 1   0E   FF   1   1     1      1   1   0      1       1
 0   0E   FF   1   0     1      1   1   0      1       1
 1   0E   FF   1   0     1      1   1   0      1       1
 0   0E   FF   1   1     1      1   1   0      1       1

 1   11   FF   0   1     1      1   1   1      1       1
 0   11   7E   0   0     1      1   0   1      1       1
 1   11   7E   0   0     1      1   0   1      1       1
 0   11   7E   0   0     1      1   0   1      1       1
 1   0F   FF   1   1     1      1   1   0      1       1
 0   0F   FF   1   0     1      1   1   0      1       1
 1   0F   FF   1   0     1      1   1   0      1       1
 0   0F   FF   1   1     1      1   1   0      1       1

 1   FD   FF   1   1     1      1   1   1      1       1
 0   FD   00   1   0     1      1   0   1      1       1
 1   FD   00   1   0     1      1   0   1      1       1
 0   FD   00   1   0     1      1   0   1      1       1
 1   FD   00   1   0     1      1   0   1      1       1
 0   FD   FF   1   1     1      1   1   1      1       1

 1   FD   FF   1   1     1      1   1   1      1       1
 0   FD   FF   1   1     1      1   1   1      1       1